Designing integrated circuits (ICs), e.g., field programmable gate arrays (FPGAs), is a complicated tasks. Many times, a logical design for the ICs or FPGAs may be very large in scope that may include many sub-level designs.
Current methodologies for IP reuse and hierarchical design flows rely on a significant number of manual steps and advanced knowledge of the design tools and various internal flows. In addition, a detailed understanding of the entire design is required to be able to successfully complete these design runs. In other words, current methodologies require that the top level end users and the design developers have intimate knowledge on both sides. Manually switching between multiple constraint files is also required to achieve the desired results.
Furthermore, current methodologies rely on custom files that may be different for different flow points. This results in many necessary files being separate from one another.